Formal Verification

Underspecified harnesses and interleaved bugs

This paper presents a technique to find interleaved bugs even with incomplete harness.

Reactivity in SystemC Transaction-Level Models

SystemC is a popular language used in modeling system-on-chip implementations. To support this task at a high level of abstraction, transaction-level modeling (TLM) libraries have been recently developped. While TLM libraries are useful, it is …